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19-4773; Rev 0; 7/98
KIT ATION EVALU BLE AVAILA
Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface
General Description Features
o 12-Bit Resolution, 1/2 LSB Linearity o +5V Single-Supply Operation o I2C-Compatible, 2-Wire Serial Interface o Four Software-Selectable Input Ranges MAX127: 0 to +10V, 0 to +5V, 10V, 5V MAX128: 0 to +VREF, 0 to +VREF/2, VREF, VREF/2 o 8 Analog Input Channels o 8ksps Sampling Rate o 16.5V Overvoltage-Tolerant Input Multiplexer o Internal 4.096V or External Reference o Two Power-Down Modes o 24-Pin Narrow DIP or 28-Pin SSOP Packages
MAX127/MAX128
The MAX127/MAX128 are multirange, 12-bit data acquisition systems (DAS) that require only a single +5V supply for operation, yet accept signals at their analog inputs that may span above the power-supply rail and below ground. These systems provide eight analog input channels that are independently software programmable for a variety of ranges: 10V, 5V, 0 to +10V, 0 to +5V for the MAX127; and VREF, VREF/2, 0 to +VREF, 0 to +VREF/2 for the MAX128. This range switching increases the effective dynamic range to 14 bits and provides the flexibility to interface 4-20mA, 12V, and 15V-powered sensors directly to a single +5V system. In addition, these converters are fault protected to 16.5V; a fault condition on any channel will not affect the conversion result of the selected channel. Other features include a 5MHz bandwidth track/hold, an 8ksps throughput rate, and the option of an internal 4.096V or external reference. The MAX127/MAX128 feature a 2-wire, I2C-compatible serial interface that allows communication among multiple devices using SDA and SCL lines. A hardware shutdown input (SHDN) and two softwareprogrammable power-down modes (standby and full power-down) are provided for low-current shutdown between conversions. In standby mode, the referencebuffer remains active, eliminating start-up delays. The MAX127/MAX128 are available in 24-pin DIP or space-saving 28-pin SSOP packages.
Typical Operating Circuit
+5V
0.1F C VDD SCL SDA
Applications
Industrial Control Systems Data-Acquisition Systems Robotics Automatic Testing Battery-Powered Instruments Medical Instruments
ANALOG INPUTS
SHDN CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
1k
MAX127 MAX128
REF REFADJ
SCL SDA A0 A1 A2 AGND
Ordering Information
PART MAX127ACNG MAX127ACNG TEMP. RANGE 0C to +70C 0C to +70C PIN-PACKAGE 24 Narrow Plastic DIP 24 Narrow Plastic DIP INL (LSB) 1/2 1
4.7F
0.01F
DGND
Ordering Information continued at end of data sheet. Pin Configurations appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
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Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface MAX127/MAX128
ABSOLUTE MAXIMUM RATINGS
VDD to AGND............................................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V CH0-CH7 to AGND ......................................................... 16.5V REF to AGND..............................................-0.3V to (VDD + 0.3V) REFADJ to AGND.......................................-0.3V to (VDD + 0.3V) A0, A1, A2 to DGND...................................-0.3V to (VDD + 0.3V) SHDN, SCL, SDA to DGND ......................................-0.3V to +6V Max Current into Any Pin ....................................................50mA Continuous Power Dissipation (TA = +70C) 24-Pin Narrow DIP (derate 13.33mW/C above +70C)..1067mW 28-Pin SSOP (derate 9.52mW/C above +70C) ...............762mW Operating Temperature Ranges MAX127_ C_ _/MAX128_ C_ _.............................0C to +70C MAX127_ E_ _/MAX128_ E_ _ ..........................-40C to +85C Storage Temperature Range ............................-65C to +150C Lead Temperature (soldering, 10sec) ............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +5V 5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7F at REF; external clock, fCLK = 400kHz; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETER ACCURACY (Note 1) Resolution Integral Nonlinearity Differential Nonlinearity INL DNL Unipolar Offset Error Bipolar Channel-to-Channel Offset Error Matching Unipolar Bipolar Unipolar Gain Error (Note 2) Bipolar Gain Tempco (Note 2) Unipolar Bipolar MAX127A/MAX128A MAX127B/MAX128B MAX127A/MAX128A MAX127B/MAX128B 3 5 MAX127A/MAX128A MAX127B/MAX128B MAX127A/MAX128A MAX127B/MAX128B 0.1 0.3 7 10 7 10 ppm/C LSB MAX127A/MAX128A MAX127B/MAX128B 12 1/2 1 1 3 5 5 10 LSB LSB Bits LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC SPECIFICATIONS (800Hz sine-wave input, 10Vp-p (MAX127) or 4.096Vp-p (MAX128), fSAMPLE = 8ksps) Signal-to-Noise plus Distortion Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Channel-to-Channel Crosstalk Aperture Delay Aperture Jitter SINAD THD SFDR 4kHz, VIN = 5V (Note 3) DC, VIN = 16.5V Up to the 5th harmonic 81 -86 -96 200 10 70 -87 -80 dB dB dB dB ns ns
2
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Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V 5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7F at REF pin; external clock, fCLK = 400kHz; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETER ANALOG INPUT Track/Hold Acquisition Time 10V or VREF range Small-Signal Bandwidth -3dB rolloff 5V or VREF/2 range 0 to 10V or 0 to VREF range 0 to 5V or 0 to VREF/2 range MAX127 Unipolar, Table 3 MAX128 Input Voltage Range VIN MAX127 Bipolar, Table 3 MAX128 MAX127 MAX128 Input Current IIN Bipolar MAX128 Input Resistance Input Capacitance INTERNAL REFERENCE REFOUT Voltage REFOUT Tempco Output Short-Circuit Current Load Regulation (Note 5) Capacitive Bypass at REF REFADJ Output Voltage REFADJ Adjustment Range Buffer Voltage Gain Figure 12 0 to 0.5mA output current 4.7 2.465 2.500 1.5 1.638 2.535 VREF TC VREF TA = +25C MAX127_C/MAX128_C MAX127_E/MAX128_E 4.076 4.096 15 30 30 10 4.116 V ppm/C mA mV F V % V/V VIN IIN Unipolar Bipolar (Note 4) MAX127 10V range 5V range VREF range VREF/2 range 0 to 10V range 0 to 5V range 0 0 0 0 -10 -5 -VREF -VREF/2 -10 -10 -10 -1200 -600 -1200 -600 21 16 40 0.1 5 2.5 2.5 1.25 10 5 VREF VREF/2 10 5 VREF VREF/2 720 360 10 720 360 10 10 k pF A V MHz 3 s SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX127/MAX128
Unipolar
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Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface MAX127/MAX128
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V 5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7F at REF pin; external clock, fCLK = 400kHz; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Input Voltage Range Input Current VREF = 4.18V Normal, or STANDBY power-down mode FULL power-down mode 10 5 VDD - 0.5 SYMBOL CONDITIONS MIN 2.4 TYP MAX 4.18 400 1 k M V UNITS V A
REFERENCE INPUT (buffer disabled, reference input applied to REF)
Input Resistance REFADJ Threshold for Buffer Disable POWER REQUIREMENTS Supply Voltage VDD
Normal or STANDBY power-down mode FULL power-down mode
4.75 Normal mode, bipolar ranges Normal mode, unipolar ranges STANDBY power-down mode (Note 6) FULL power-down mode External reference = 4.096V Internal reference 6 700 120 0.1 0.5
5.25 18 10 850 220 0.5
V mA A LSB
Supply Current
IDD
Power-Supply Rejection Ratio (Note 7) TIMING External Clock Frequency Range Conversion Time Throughput Rate Bandgap Reference Start-Up Time Reference Buffer Settling Time
PSRR
fCLK tCONV 6.0 7.7
0.4 10.0 8 Power-up (Note 8) To 0.1mV, REF bypass capacitor fully discharged CREF = 4.7F CREF = 33F 200 8 60 2.4 0.8 VIN = 0 or VDD (Note 4) 0.2 0.1 10 15
MHz s ksps s ms
DIGITAL INPUTS (SHDN, A2, A1, A0) Input High Threshold Voltage Input Low Threshold Voltage Input Leakage Current Input Capacitance Input Hysteresis VIH VIL IIN CIN VHYS V V A pF V
4
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Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V 5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7F at REF pin; external clock, fCLK = 400kHz; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETER DIGITAL INPUTS (SDA, SCL) Input High Threshold Voltage Input Low Threshold Voltage Input Hysteresis Input Leakage Current Input Capacitance DIGITAL OUTPUTS (SDA) Output Low Voltage Three-State Output Capacitance VOL COUT ISINK = 3mA ISINK = 6mA (Note 4) 0.4 0.6 15 V pF VIH VIL VHYS IIN CIN VIN = 0 or VDD (Note 4) 0.3 x VDD 0.05 x VDD 0.1 10 15 0.7 x VDD V V V A pF SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX127/MAX128
TIMING CHARACTERISTICS
(VDD = +4.75V to +5.25V; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7F at REF pin; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETERS 2-WIRE FAST MODE 2-WIRE FAST MODE SCL Clock Frequency Bus Free Time Between a STOP and START Condition Hold Time (Repeated) START Condition Low Period of the SCL Clock High Period of the SCL Clock Set-Up Time for a Repeated START Condition Data Hold Time Data Setup Time Rise Time for Both SDA and SCL Signals (Receiving) Fall Time for Both SDA and SCL Signals (Receiving) Fall Time for Both SDA and SCL Signals (Transmitting) Set-Up Time for STOP Condition Capacitive Load for Each Bus Line Pulse Width of Spike Suppressed fSCL tBUF tHD,STA tLOW tHIGH tSU,STA tHD,DAT tSU,DAT tR tF tF tSU,STO Cb tSP 0 Cb = Total capacitance of one bus line in pF Cb = Total capacitance of one bus line in pF Cb = Total capacitance of one bus line in pF 1.3 0.6 1.3 0.6 0.6 0 100 20 + 0.1 x Cb 20 + 0.1 x Cb 20 + 0.1 x Cb 0.6 400 50 300 300 250 0.9 400 kHz s s s s s s ns ns ns ns s pF ns SYMBOL CONDITIONS MIN TYP MAX UNITS
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Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface MAX127/MAX128
TIMING CHARACTERISTICS (continued)
(VDD = +4.75V to +5.25V; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7F at REF pin; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETERS 2-WIRE STANDARD MODE SCL Clock Frequency Bus Free Time Between a STOP and START Condition Hold Time (Repeated) START Condition Low Period of the SCL Clock High Period of the SCL Clock Setup Time for a Repeated START Condition Data Hold Time Data Setup Time Rise Time for Both SDA and SCL Signals (Receiving) Fall Time for Both SDA and SCL Signals (Receiving) Fall Time for Both SDA and SCL Signals (Transmitting) Setup Time for STOP Condition Capacitive Load for Each Bus Line Pulse Width of Spike Suppressed Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: fSCL tBUF tHD,STA tLOW tHIGH tSU, STA tHD, DAT tSU, DAT tR tF tF tSU, STO Cb tSP 0 Cb = total capacitance of one bus line in pF, up to 6mA sink 20 + 0.1 x Cb 4.0 400 50 4.7 4.0 4.7 4.0 4.7 0 250 1000 300 250 0.9 100 kHz s s s s s s ns ns ns ns s pF ns SYMBOL CONDITIONS MIN TYP MAX UNITS
Accuracy specifications tested at VDD = 5.0V. Performance at power-supply tolerance limits is guaranteed by PowerSupply Rejection test. External reference: VREF = 4.096V, offset error nulled, ideal last-code transition = FS - 3/2LSB. Ground "on" channel, sine wave applied to all "off" channels. Guaranteed by design. Not tested. Use static external load during conversion for specified accuracy. Tested using internal reference. PSRR measured at full scale. Tested for the 10V (MAX127) and 4.096V (MAX128) input ranges. Not subject to production testing. Provided for design guidance only.
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Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface
Typical Operating Characteristics
(VDD = +5V, external reference mode, VREF = 4.096V; 4.7F at REF; external clock, fCLK = 400kHz; TA = +25C; unless otherwise noted.)
STANDBY SUPPLY CURRENT vs. TEMPERATURE
MAX127/8-02 MAX127/8-03
MAX127/MAX128
SUPPLY CURRENT vs. SUPPLY VOLTAGE
max127/8-01
SUPPLY CURRENT vs. TEMPERATURE
6.5 750 STANDBY SUPPLY CURRENT (A) 650 550 450 350 250 150
25
20 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA)
6.3
INTERNAL REFERENCE
15
6.1
10
5.9
5
5.7
EXTERNAL REFERENCE
0 0 1 2 3 4 5 6 7 SUPPLY VOLTAGE (V)
5.5 -40 -15 10 35 60 85 TEMPERATURE (C)
50 -40 -15 10 35 60 85 TEMPERATURE (C)
CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING (LSB)
FULL POWER-DOWN SUPPLY CURRENT vs. TEMPERATURE
MAX127/8-04
NORMALIZED REFERENCE VOLTAGE vs. TEMPERATURE
MAX127/8-05
CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING vs. TEMPERATURE
BIPOLAR MODE
MAX127/8-06
FULL POWER-DOWN SUPPLY CURRENT (A)
150 130
1.001 NORMALIZED REFERENCE VOLTAGE 1.000
0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 -40 -15 10
EXTERNAL REFERENCE
110
0.999
90 INTERNAL REFERENCE
0.998
70
0.997
UNIPOLAR MODE
50 -40 -15 10 35 60 85 TEMPERATURE (C)
0.996 -40 -15 10 35 60 85 TEMPERATURE (C)
35
60
85
TEMPERATURE (C)
CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING (LSB)
CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING vs. TEMPERATURE
MAX127/8-07
INTEGRAL NONLINEARITY vs. DIGITAL CODE
MAX127/8-08
FFT PLOT
VDD = 5V fIN = 800Hz fSAMPLE = 8kHz
MAX127/8-09
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 -40 -15 10 35 60 UNIPOLAR MODE
0.15 INTEGRAL NONLINEARITY (LSB) 0.10 0.05 0 -0.05 -0.10 -0.15
0 -20 AMPLITUDE (dB) -40 -60 -80 -100 -110
BIPOLAR MODE
85
0
819
1638
2457
3276
4095
0
800
1600
2400
3200
4000
TEMPERATURE (C)
DIGITAL CODE
FREQUENCY (Hz)
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Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface MAX127/MAX128
Pin Description
PIN DIP 1, 2 3, 9, 22, 24 4 5 6, 8, 10 7 SSOP 1, 2 4, 7, 8, 11, 22, 24, 25, 28 3 5 6, 10, 12 9 NAME VDD N.C. DGND SCL A0, A2, A1 SDA FUNCTION +5V Supply. Bypass with a 0.1F capacitor to AGND. No Connect. No internal connection. Digital Ground Serial Clock Input Address Select Inputs Open-Drain Serial Data I/O. Input data is clocked in on the rising edge of SCL, and output data is clocked out on the falling edge of SCL. External pull-up resistor required. Shutdown Input. When low, device is in full power-down (FULLPD) mode. Connect high for normal operation. Analog Ground Analog Input Channels Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with a 0.01F capacitor to AGND. Connect to VDD when using an external reference at REF. Reference Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer provides a 4.096V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal reference by pulling REFADJ to VDD and applying the external reference to REF.
11 12 13-20 21
13 14 15-21, 23 26
SHDN AGND CH0-CH7 REFADJ
23
27
REF
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Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface MAX127/MAX128
SDA A2 A1 A0 SCL
SHDN CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 REF
SERIAL INTERFACE LOGIC
INT CLOCK
ANALOG INPUT MUX AND SIGNAL CONDITIONING
VDD AGND DGND
OUT T/H IN
CLOCK 12-BIT SAR ADC
REF
2.5V REFERENCE REFADJ
10k
AV = 1.638
MAX127 MAX128
Figure 1. Block Diagram
Detailed Description
BIPOLAR
Converter Operation
The MAX127/MAX128 multirange, fault-tolerant ADCs use successive approximation and internal track/hold (T/H) circuitry to convert an analog signal to a 12-bit digital output. Figure 1 shows the block diagram for these devices.
5.12k R1 CH_
S1 UNIPOLAR OFF CHOLD S2 ON R2 HOLD S3 TRACK TRACK
VOLTAGE REFERENCE
Analog-Input Track/Hold
The T/H circuitry enters its tracking/acquisition mode on the falling edge of the sixth clock in the 8-bit input control word and enters its hold/conversion mode when the master issues a STOP condition. For timing information, see the Start a Conversion section.
T/H OUT HOLD S4
Input Range and Protection
The MAX127/MAX128 have software-selectable input ranges. Each analog input channel can be independently programmed to one of four ranges by setting the appropriate control bits (RNG, BIP) in the control byte (Table 1). The MAX127 has selectable input ranges extending to 10V (VREF x 2.441), while the MAX128 has selectable input ranges extending to VREF. Note that when an external reference is applied at REFADJ, the voltage at REF is given by VREF = 1.638 x VREFADJ (2.4 < V REF < 4.18). Figure 2 shows the equivalent input circuit. A resistor network on each analog input provides a 16.5V fault protection for all channels. This circuit limits the current going into or out of the pin to less than 1.2mA, whether or not the channel is on. This provides an added layer of protection when momentary overvoltages occur at the selected input channel, and when a negative signal is applied at the input even though
S1 = BIPOLAR/UNIPOLAR SWITCH S2 = INPUT MUX SWITCH S3, S4 = T/H SWITCH
R1 = 12.5k (MAX127) OR 5.12k (MAX128) R2 = 8.67k (MAX127) OR (MAX128)
Figure 2. Equivalent Input Circuit
the device may be configured for unipolar mode. Overvoltage protection is active even if the device is in power-down mode or VDD = 0.
Digital Interface
The MAX127/MAX128 feature a 2-wire serial interface consisting of the SDA and SCL pins. SDA is the data I/O and SCL is the serial clock input, controlled by the master device. A2-A0 are used to program the MAX127/MAX128 to different slave addresses. (The MAX127/MAX128 only work as slaves.) The two bus lines (SDA and SCL) must be high when the bus is not in use. External pull-up resistors (1kor greater) are required on SDA and SCL to maintain I2C compatibility. Table 1 shows the input control-byte format.
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Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface MAX127/MAX128
Table 1. Control-Byte Format
BIT 7 (MSB) START BIT 7 (MSB) 6, 5, 4 3 2 1, 0 (LSB) BIT 6 SEL2 NAME START SEL2, SEL1, SEL0 RNG BIP PD1, PD0 BIT 5 SEL1 BIT 4 SEL0 BIT 3 RNG BIT 2 BIP BIT 1 PD1 BIT 0 (LSB) PD0
DESCRIPTION The logic "1" received after acknowledge of a write bit (R/W = 0) defines the beginning of the control byte. These three bits select the desired "ON" channel (Table 2). Selects the full-scale input voltage range (Table 3). Selects unipolar or bipolar conversion mode (Table 3). These two bits select the power-down modes (Table 4).
Table 2. Channel Selection
SEL2 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 CHANNEL CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
Table 4. Power-Down and Clock Selection
PD1 0 1 1 PD0 X 0 1 MODE Normal Operation (always on) Standby Power-Down Mode (STBYPD) Full Power-Down Mode (FULLPD)
Table 3. Range and Polarity Selection
INPUT RANGE (V) MAX127 0 to 5 0 to 10 5 10 MAX128 0 to VREF/2 0 to VREF VREF/2 VREF 0 1 0 1 0 0 1 1 - - -VREF/2 -VREF 0 0 0 0 VREF/2 VREF VREF/2 VREF 0 1 0 1 0 0 1 1 - - -VREF x 1.2207 -VREF x 2.4414 0 0 0 0 VREF x 1.2207 VREF x 2.4414 VREF x 1.2207 VREF x 2.4414 RNG BIP NEGATIVE FULL SCALE (V) ZERO SCALE (V) FULL SCALE (V)
10
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Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface
Slave Address
The MAX127/MAX128 have a 7-bit-long slave address. The first four bits (MSBs) of the slave address have been factory programmed and are always 0101. The logic state of the address input pins (A2-A0) determine the three LSBs of the device address (Figure 3). A maximum of eight MAX127/MAX128 devices can therefore be connected on the same bus at one time. A2-A0 may be connected to V DD or DGND, or they may be actively driven by TTL or CMOS logic levels. The eighth bit of the address byte determines whether the master is writing to or reading from the MAX127/ MAX128 (R/W = 0 selects a write condition. R/W = 1 selects a read condition).
Conversion Control
The master signals the beginning of a transmission with a START condition (S), which is a high-to-low transition on SDA while SCL is high. When the master has finished communicating with the slave, the master issues a STOP condition (P), which is a low-to-high transition on SDA while SCL is high (Figure 4). The bus is then free for another transmission. Figure 5 shows the timing diagram for signals on the 2-wire interface. The address-byte, control-byte, and data-byte are transmitted between the START and STOP conditions. The SDA state is allowed to change only while SCL is low, except for the START and STOP conditions. Data is transmitted in 8-bit words. Nine clock cycles are required to transfer the data in or out of the MAX127/MAX128. (Figures 9 and 10).
MAX127/MAX128
SLAVE ADDRESS 0 SDA LSB SCL SCL START CONDITION SLAVE ADDRESS BITS A2, A1, AND A0 CORRESPOND TO THE LOGIC STATE OF THE ADDRESS INPUT PINS A2, A1, AND A0. STOP CONDITION 1 0 1 A2 A1 A0 R/W ACK SDA
Figure 3. Address Byte
Figure 4. START and STOP Conditions
SDA tSU, DAT tLOW SCL tHD, STA tR START CONDITION tHIGH tF REPEATED START CONDITION STOP CONDITION START CONDITION tHD, DAT tSU, STA tHD, STA tSU, STO tBUF
Figure 5. 2-Wire Serial-Interface Timing Diagram
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Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface
Start a Conversion (Write Cycle) A conversion cycle begins with the master issuing a START condition followed by seven address bits (Figure 3) and a write bit (R/W = 0). Once the eighth bit has been received and the address matches, the MAX127/MAX128 (the slave) issues an acknowledge by pulling SDA low for one clock cycle (A = 0). The master then writes the input control byte to the slave (Figure 8). After this byte of data, the slave issues another acknowledge, pulling SDA low for one clock cycle. The master ends the write cycle by issuing a STOP condition (Figure 6). When the write bit is set (R/W = 0), acquisition starts as soon as Bit 2 (BIP) of the input control-byte has been latched and ends when a STOP condition has been issued. Conversion starts immediately after acquisition. The MAX127/MAX128's internal conversion clock frequency is 1.56MHz, resulting in a typical conversion time of 7.7s. Figure 9 shows a complete write cycle. Read a Conversion (Read Cycle) Once a conversion starts, the master does not need to wait for the conversion to end before attempting to read the data from the slave. Data access begins with the master issuing a START condition followed by a 7-bit address (Figure 3) and a read bit (R/W = 1). Once the eighth bit has been received and the address matches, the slave issues an acknowledge by pulling low on SDA for one clock cycle (A = 0) followed by the first byte of serial data (D11-D4, MSB first). After the first byte has been issued by the slave, it releases the bus for the master to issue an acknowledge (A = 0). After receiving the acknowledge, the slave issues the second byte (D3-D0 and four zeros) followed by a NOT acknowledge (A = 1) from the master to indicate that the last data byte has been received. Finally, the master issues a STOP condition (P), ending the read cycle (Figure 7).
MAX127/MAX128
1 7 11 8 11 S SLAVE ADDRESS W A CONTROL-BYTE A P START CONDITION WRITE ACKNOWLEDGE
MASTER TO SLAVE SLAVE TO MASTER NO. OF BITS
STOP CONDITION ACKNOWLEDGE
Figure 6. Write Cycle
MASTER TO SLAVE SLAVE TO MASTER 1 7 11 8 1 8 11 S SLAVE ADDRESS R A DATA-BYTE A DATA-BYTE A P ACKNOWLEDGE READ NO. OF BITS
START CONDITION
STOP CONDITION NOT ACKNOWLEDGE
Figure 7. Read Cycle
START SEL2 SDA MSB SCL START: ACK:
SEL1 SEL0
RNG
BIP
PD1
PD0
ACK
LSB
FIRST LOGIC "1" RECEIVED AFTER ACKNOWLEDGE OF A WRITE. ACKNOWLEDGE BIT. THE MAX127/MAX128 PULL SDA LOW DURING THE 9TH CLOCK PULSE.
Figure 8. Command Byte
SLAVE ADDRESS BYTE 0 SDA MSB SCL A/D STATE START CONDITION 1 2 7 1 W LSB 8 A S MSB 9 10 11
CONTROL BYTE BIP PD1 PD0 LSB 15 16 17 18 CONVERSION STOP CONDITION A
ACQUISITION
Figure 9. Complete 2-Wire Serial Write Transmission
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Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface MAX127/MAX128
SLAVE ADDRESS BYTE 0 MSB 1 START CONDITION 2 7 1 R LSB 8 A
MSB DATA BYTE
LSB DATA BYTE FILLED WITH 4 ZEROS LSB 22 23 26 27 STOP CONDITION
D11 MSB 10 11
D4 LSB 17
A
D3 MSB 19
D0
A
9
18
Figure 10. Complete 2-Wire Serial Read Transmission
The MAX127/MAX128 ignore acknowledge and NOTacknowledge conditions issued by the master during the read cycle. The device waits for the master to read the output data or waits until a STOP condition is issued. Figure 10 shows a complete read cycle. In unipolar input mode, the output is straight binary. For bipolar input mode, the output is two's complement. For output binary codes see the Transfer Function section.
External Reference To use the REF input directly, disable the internal buffer by connecting REFADJ to VDD (Figure 11b). Using the REFADJ input eliminates the need to buffer the reference externally. When the reference is applied at REFADJ, bypass REFADJ with a 0.01F capacitor to AGND (Figure 11c).
At REF and REFADJ, the input impedance is a minimum of 10k for DC currents. During conversions, an external reference at REF must be able to drive a 400A DC load, and must have an output impedance of 10 or less. If the reference has higher input impedance or is noisy, bypass REF with a 4.7F capacitor to AGND as close to the chip as possible. With an external reference voltage of less than 4.096V at REF or less than 2.5V at REFADJ, the increase in RMS noise to the LSB value (full-scale voltage/4096) results in performance degradation and loss of effective bits.
Applications Information
Power-On Reset
The MAX127/MAX128 power up in normal operating mode, waiting for a START condition followed by the appropriate slave address. The contents of the input and output data registers are cleared at power-up.
Internal or External Reference
The MAX127/MAX128 operate with either an internal or an external reference (Figures 11a-11c). An external reference is connected to either REF or to REFADJ. The REFADJ internal buffer gain is trimmed to 1.6384 to provide 4.096V at REF from a 2.5V reference.
Power-Down Mode
To save power, put the converter into low-current shutdown mode between conversions. Two programmable power-down modes are available, in addition to the hardware shutdown. Select STBYPD or FULLPD by programming PD0 and PD1 in the input control byte (Table 4). When software power-down is asserted, it becomes effective only after the end of conversion. In all powerdown modes, the interface remains active and conversion results may be read. Input overvoltage protection is active in all power-down modes.
Internal Reference The internally trimmed 2.50V reference is amplified through the REFADJ buffer to provide 4.096V at REF. Bypass REF with a 4.7F capacitor to AGND and bypass REFADJ with a 0.01F capacitor to AGND (Figure 11a). The internal reference voltage is adjustable to 1.5% (65 LSBs) with the reference-adjust circuit of Figure 12.
______________________________________________________________________________________
13
Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface MAX127/MAX128
REF CREF 4.7F 100k REFADJ 0.01F 10k 0.01F 24k
MAX127 MAX128
AV = 1.638
+5V 510k REFADJ
MAX127 MAX128
2.5V
Figure 11a. Internal Reference
Figure 12. Reference-Adjust Circuit
REF
4.096V CREF 4.7F
MAX127 MAX128
AV = 1.638 REFADJ 10k
VDD
To power-up from a software initiated power-down, a START condition followed by the correct slave address must be received (with R/W = 0). The MAX127/MAX128 power-up after receiving the next bit. For hardware-controlled power-down (FULLPD), pull SHDN low. When hardware shutdown is asserted, it becomes effective immediately and any conversion in progress is aborted.
Choosing Power-Down Modes
The bandgap reference and reference buffer remain active in STBYPD mode, maintaining the voltage on the 4.7F capacitor at REF. This is a "DC" state that does not degrade after standby power-down of any duration. In FULLPD mode, only the bandgap reference is active. Connect a 33F capacitor between REF and AGND to maintain the reference voltage between conversions and to reduce transients when the buffer is enabled and disabled. Throughput rates down to 1ksps can be achieved without allotting extra acquisition time for reference recovery prior to conversion. This allows conversion to begin immediately after power-down ends. If the discharge of the REF capacitor during FULLPD exceeds the desired limits for accuracy (less than a fraction of an LSB), run a STBYPD power-down cycle prior to starting conversions. Take into account that the reference buffer recharges the bypass capacitor at an 80mV/ms slew rate, and add 50s for settling time.
2.5V
Figure 11b. External Reference, Reference at REF
REF
MAX127 MAX128
AV = 1.638 REFADJ 10k
CREF 4.7F
2.5V 0.01F
2.5V
Auto-Shutdown Selecting STBYPD on every conversion automatically shuts the MAX127/MAX128 down after each conversion without requiring any start-up time on the next conversion.
Figure 11c. External Reference, Reference at REFADJ
14
______________________________________________________________________________________
Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface
Transfer Function
Output data coding for the MAX127/MAX128 is binary in unipolar mode with 1LSB = (FS/4096) and two's complement binary in bipolar mode with 1LSB = [(2 x | FS | ) / 4096]. Code transitions occur halfway between successive-integer LSB values. Figures 13a and 13b show the input/output (I/O) transfer functions for unipolar and bipolar operations, respectively. For full-scale (FS) values, refer to Table 3.
OUTPUT CODE 11... 111 11... 110 11... 101 FULL-SCALE TRANSITION 1 LSB = FS 4096
Layout, Grounding, and Bypassing
Careful printed circuit board layout is essential for best system performance. For best performance, use a ground plane. To reduce crosstalk and noise injection, keep analog and digital signals separate. Connect analog grounds and DGND in a star configuration to AGND. For noise-free operation, ensure the ground return from AGND to the supply ground is low impedance and as short as possible. Connect the logic grounds directly to the supply ground. Bypass VDD with 0.1F and 4.7F capacitors to AGND to minimize highand low-frequency fluctuations. If the supply is excessively noisy, connect a 5 resistor between the supply and VDD, as shown in Figure 14.
MAX127/MAX128
SUPPLY +5V GND
4.7F
00... 011 00... 010 00... 001 00... 000 0 1 2 3 INPUT VOLTAGE (LSB) FS - 3/2 LSB FS
R* = 5 0.1F ** VDD AGND DGND +5V DGND
MAX127 MAX128
DIGITAL CIRCUITRY
Figure 13a. Unipolar Transfer Function
OUTPUT CODE 1 LSB = 011... 111 011... 110
* OPTIONAL ** CONNECT AGND AND DGND WITH A GROUND PLANE OR A SHORT TRACE.
2FS 4096
Figure 14. Power-Supply Grounding Connection
000... 001 000... 000 111... 111
100... 010 100... 001 100... 000 -FS 0 INPUT VOLTAGE (LSB) +FS - 1 LSB
Figure 13b. Bipolar Transfer Function
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Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface MAX127/MAX128
Ordering Information (continued)
PART MAX127ACAI MAX127BCAI TEMP. RANGE 0C to +70C 0C to +70C PIN-PACKAGE 28 SSOP 28 SSOP 24 Narrow Plastic DIP 24 Narrow Plastic DIP 28 SSOP 28 SSOP 24 Narrow Plastic DIP 24 Narrow Plastic DIP 28 SSOP 28 SSOP 24 Narrow Plastic DIP 24 Narrow Plastic DIP 28 SSOP 28 SSOP INL (LSB) 1/2 1 1/2 1 1/2 1 1/2 1 1/2 1 1/2 1 1/2 1
Chip Information
TRANSISTOR COUNT: 4219 SUBSTRATE CONNECTED to AGND
MAX127AENG -40C to +85C MAX127BENG -40C to +85C MAX127AEAI MAX127BEAI MAX128ACNG MAX128BCNG MAX128ACAI MAX128BCAI -40C to +85C -40C to +85C 0C to +70C 0C to +70C 0C to +70C 0C to +70C
MAX128AENG -40C to +85C MAX128BENG -40C to +85C MAX128AEAI MAX128BEAI -40C to +85C -40C to +85C
Pin Configurations
TOP VIEW
VDD 1 VDD 2 DGND 3 N.C. 4 SCL 5 A0 6 N.C. 7 N.C. 8 SDA 9 A2 10 N.C. 11 A1 12 SHDN 13 AGND 14 28 N.C. 27 REF 26 REFADJ 25 N.C. 24 N.C. VDD 1 VDD 2 N.C. 3 DGND 4 SCL 5 A0 6 SDA 7 A2 8 N.C. 9 A1 10 SHDN 11 AGND 12 24 N.C. 23 REF 22 N.C. 21 REFADJ
MAX127 MAX128
23 CH7 22 N.C. 21 CH6 20 CH5 19 CH4 18 CH3 17 CH2 16 CH1 15 CH0
MAX127 MAX128
20 CH7 19 CH6 18 CH5 17 CH4 16 CH3 15 CH2 14 CH1 13 CH0
DIP SSOP
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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